Tutorial 1

RISC-V, Present and Future

Morris Hung, 洪彰辰

Deputy Director, Business Development of IPBU, Andes Technology Corporation,

業務開發處副處長, 晶心科技

2020年8月4日(二) 19:00~20:00




RISC-V is changing the processor landscape rapidly when entering a new golden age for computer architecture. Being open, modular yet compact and innovative RISC-V is the game-changer. Andes will present the overview of RISC-V International, ISA, and ecosystem followed by Andes company profile and product portfolio. Through extensive customer engagement and successful stories, Andes will reveal the transformation of processor landscape and share how Andes exploit its technologies to greatly improve performance and efficiency when building Domain-Specific Architectures.



Morris Hung is Deputy Director, Business Development of IPBU at Andes. He is building relationship with key account executives and also driving RISC-V ecosystem with partners and OEMs. With a background in computer science, low-power connectivity, digital power in mobile and embedded systems, he accelerates customer adoption of  best-in-class Andes RISC-V cores and develops business strategy to increase sales revenue. Prior to Andes, he was Lead FAE in Dialog Semiconductor and worked with world-leading customers in Taiwan. He received his master's degree in Electrical Engineering from Curtin University in Perth WA.

Tutorial 2

Design and Challenges of 50+Gb/s PAM-4 Transceivers for Next-Generation Wireline Communication

Pen-Jui Peng, 彭朋瑞

Assistant Professor, Yuan Ze University, 元智大學電機系助理教授

2020年8月4日(二) 20:00~21:00




The data format has been transferred from non-return-to-zero (NRZ) to 4-level pulse amplitude modulation (PAM-4) for ultra-high-speed wireline applications due to its two-fold bandwidth efficiency. However, the non-idealities in PAM-4 signal are more significant than the NRZ counterpart both in the transmitter and receiver design. This tutorial talks about the design and challenges for the PAM-4 transceivers to achieve 50+Gb/s data rate for the next-generation wireline applications.



Pen-Jui Peng received the B.S. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2008, the M.S. degree from the Graduate Institute of Communication Engineering, NTU, Taipei, Taiwan, in 2010, and the Ph.D. degree from the Graduate Institute of Electronics Engineering (GIEE), NTU, Taipei, Taiwan, in 2015.

From 2015 to 2016, he was a Post-Doctoral Research Fellow with the GIEE, NTU, Taipei, Taiwan. In February 2016, he joined the faculty of the Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan, where he is currently an Assistant Professor. His research interests include high-speed SerDes transceivers, phase-locked loops, high-speed data converters, wireless transceivers, and electrical integrated circuits for silicon photonics.

Dr. Peng has received a Yong Scholar Fellowship from the Ministry of Science and Technology (MOST) in Taiwan for 5-year research funding (2018~2023).