Oral Sessions

Neuromorphic engineering refers to modeling nervous systems and realizing the model as a system-on-a-chip (SoC). This paper presents a neuromorphic chip fabricated by the standard CMOS 28nm technology, occupying a chip area of 4.5mm2. It provides 32 input neurons, 32 output neurons, and 32x32 synapses. Each synapse has its weight stored in 8-bit static random access memory (SRAM), and the weight is adaptable online by the spike-time-dependent plasticity (STDP) learning rule. The system architecture, sub-circuits architecture, and pilot measurement results are presented and discussed in this paper.

 

Parallelization is a common design practice for throughput improvement on multicore systems. However, the existing operating systems’ schedulers for CNN inference essentially divide the computational tasks of each convolution layer onto different CPU cores and cause significant inter-core feature-map data movement. Therefore, the overall performance is often degraded. In this paper, we propose a pipeline-based scheduler for convolution neural network inference parallelization with minimal feature-map data movement requirements. The experimental results show that our approach can achieve 73% performance improvement on throughput compared to the existing multi-thread scheduler.

 

The Convolutional Neural Network (CNN) has been proven its efficient to solve classification and recognition problems in recent years. However, due to the high computational complexity and high diverse dataflow, the CNN hardware implementation becomes a big design challenge. In conventional way, the designers usually implement a dedicated hardware based on specific CNN models or specific CNN layers, which decreases the design flexibility significantly. To mitigate the design challenge of CNN hardware implementation, we propose a novel Lego-based CNN design paradigm. Because each different CNN model is composed of similar computing functions with varying hyperparameters and dataflow, the design complexity depends on the interconnection between each computing function unit. Consequently, in this paper, we involve the Network-on-Chip (NoC) interconnection to connect each pre-defined computing function (e.g., convolution, pooling, etc.), which is called Neu-Lego. Due to the characteristic of high-flexible NoC interconnection, the corresponding Neu-Lego can transmit the data through packet delivery. In this way, the different large-scale and high-diverse CNN models can be composed by several interconnected Neu-Lego blocks without changing the interconnection, which increases the design flexibility. Therefore, our design has better compatibility because of the flexible on-chip interconnection. In addition, we propose a mapping algorithm to map the Lego PE to reduce the data communication on the NoC. Compared with the conventional approaches, the proposed mapping can improve 7.44% to 202.34% throughput and reduce 38.65% to 63.84% traffic latency, according to different involved CNN models and mapping algorithms.

 

* Abstract is not available.