Oral Sessions

This work presents a support vector machine (SVM) seizure detector that aims at epileptic seizure control with both seizure detection and on-chip model adaptation. Alternating direction method of multipliers (ADMM) is employed for highly- parallel SVM training. From the perspective of algorithm, minimum-redundancy maximum-relevance (mRMR) and low- rank approximation are exploited to reduce overall computational complexity by 99.4% while also reducing memory storage by 90.4%. From the aspect of hardware optimization, by utilizing hardware-shared configurable CORDIC-based processing element array, overall hardware complexity is reduced by 87%. The training latency is reduced by 98.6% by adopting parallel rotations and folded structure for approximate Jacobi method. The chip achieves detection performance with a 96.6% accuracy and a 0.28/hour false alarm rate within 0.71 seconds with power dissipation of 1.9 mW. Compared to other state-of-the-art seizure detectors, the proposed design achieves the shortest detection latency. It also supports real-time on-chip model adaptation with a latency of 0.78 seconds. This work achieves a 22× higher throughput and a 162× higher energy efficiency for SVM training compared to previous designs.

 

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A combination of the median filter and local binary patterns feature extraction architecture is proposed in this paper. However, the filtered result will be stored in the storage element and sent to the next feature extraction. Based on both are spatial domain algorithms, using parallel and pipeline to achieve synchronous operation. Change the pixel input to column vector input and omit the storage process. Use median filters or hybrid median filters combined with local binary patterns and compare FPGA hardware resource usage. Because the two filters have different algorithms and sorting methods, the Hybrid median filter uses nearly half the hardware resources of the Median filter.

 

Autonomous micro robots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path planning processor for 2D/3D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly-exploring random tree (RRT) algorithm to ensure efficient planning on maps with a higher dimension and a higher resolution. Dual-tree planning, branch extension, and parallel expansion are adopted to reduce both computational complexity and memory requirement. A prune-and-reuse strategy is also adopted to quickly respond to dynamic scenarios. Fabricated in a 40-nm CMOS technology, the chip integrates 2M logic gates in 3.65 mm2 area. It supports path planning tasks on both 2D and 3D maps, with latencies of less than 1 and 10 ms, respectively. For a 100x100 2D map, the proposed processor dissipates 1.5 J/task at a clock frequency of 200 MHz from a 0.9-V supply. Compared to the state-of-the-art designs, the proposed path planning processor achieves a 1467 shorter processing latency with 2133 lower energy dissipation, despite the capability for larger maps.