Oral Sessions

A power-efficient differential-to-single-ended au- tonomous current adaptation buffer amplifier (ACABA) with capacitive feedback topology, rail-to-rail input and output swing ranges is proposed. The ACABA gain can be adjusted through the capacitor array. By programming charge on the floating gate transistor, the input offset and bandwidth can be tuned. The main amplifier employs two-stage super class-AB structure. An inverted class-AB input stage with recycling folded-cascode is followed by a class-AB output stage with a folded mesh and a simple minimum selector. A prototype ACABA has been designed and fabricated in a 0.35 μm CMOS process occupying an area of 0.109 mm2 with variable gain and with rail-to-rail input and output swing ranges. When loaded by a 1 nF capacitor, it consumes 25.35 μW to achieve a gain-bandwidth product of 100 kHz with measured IIP3 of 39.21 dBV and a slew rate of 0.5V/ μs.

 

A CMOS capsaicin concentration converter with auto-sensitivity control circuits is newly used for sensing Scoville scale applications. The proposed converter can transform capsaicin concentration into duty cycle linearly. In addition, the auto-sensitivity control circuits could automatically adjust the sensitivities under different capsaicin concentration intervals. For some patients, under low capsaicin concentration, harmful issues become an important issue for human body. With this functionality of auto-sensitivity control circuits, it can detect capsaicin concentration more sensitivity under low capsaicin concentration. The input differential voltage range of this proposed converter was from 0.1 to 1.4 V, and the corresponding range of output duty cycle was 12.223 to 95.555 %. The sensitivities of the whole system were 0.064, 0.039, 0.032, 0.021, and 0.007 %/SHU. The proposed chip could be used for detecting capsaicin concentration applications.

 

* Abstract is not available.

 

This paper presents a readout circuit, which is composed of transimpedance, programmable gain amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC), for piezoelectric accelerometer. The proposed readout circuit achieves a high linearity and low power consumption by optimizing each operational amplifier according to the linearity requirement of the whole system. The differential architecture is adopted to deal with the sensed signal for the purposes of reducing the common mode noise. A SAR ADC is used to convert the analog signal to its corresponding digital code, so the sensed signal can analyze in the digital domain. For proving the proposed design, a test chip is implemented in a 0.18 μm CMOS process. At 1.8 V supply voltage and 100kS/s sampling rate, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.74 dB and a corresponding effective number of bits (ENOB) of 9.47 bit for a Nyquist input. The total power consumption is 1.9 μW, resulting a figure of merit (FoM) of 27.2 fJ/conversion-step. Combining with the piezoelectric accelerometer, the accelerometer system can achieve 5 kHz bandwidth with a 154 mv/g sensitivity and the linearity is 0.9956.