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GaN devices operating at reverse conduction region causing excessive conduction loss. Therefore, the GaN based switching converters are required to minimize the dead-time. This paper proposes a novel highly digitally adaptive dead-time control for GaN driver. A driver integrated circuit (IC) is designed in 0.18μm BCD GEN2 process to verify the concept. The simulation result achieves 0.4ns dead-time at 5A. The measurement result achieves 0.7ns deadtime at 2A and efficiency can improve 2.1% at 2A full load compared to 10ns fixed dead-time counterpart

 

In the paper, we discuss piezoelectric-vibration energy-harvesting flipping active-diode rectifiers, including the full bridge rectifier (FBR), the active diode rectifier, the switch only rectifier (SOR), and the flipping-capacitor rectifier (FCR). The energy harvesting circuits were implemented in 0.35-μm CMOS process. Compared to the transferred-power ability of the conventional FBR, the simulation improved factors of an active diode rectifier, SOR and FCR can reach up to 2x, 3.2x and 4.6x at an excitation frequency of 100 Hz, respectively.

 

This paper presents a charge pump with an embedded soil electrical conductivity (soil-EC) sensor. The sensing system harvests energy and measures the conductivity of the soil simultaneously solely using the proposed wide-range capacitive DC-DC power converter. The embedded time-domain slope detection mechanism is employed to measure conductivity and maintain high conversion efficiency. The self-sustained soil-EC monitoring IC was fabricated using 0.18-μm CMOS technology. The design achieves a tracking efficiency of 98% over an input range of 416-5000μW, a peak system conversion efficiency of 88%, and also measures the soil EC from 0.114 to 0.744 mS/cm.

 

* Abstract is not available.

 

A power-efficient differential-to-single-ended au- tonomous current adaptation buffer amplifier (ACABA) with capacitive feedback topology, rail-to-rail input and output swing ranges is proposed. The ACABA gain can be adjusted through the capacitor array. By programming charge on the floating gate transistor, the input offset and bandwidth can be tuned. The main amplifier employs two-stage super class-AB structure. An inverted class-AB input stage with recycling folded-cascode is followed by a class-AB output stage with a folded mesh and a simple minimum selector. A prototype ACABA has been designed and fabricated in a 0.35 μm CMOS process occupying an area of 0.109 mm2 with variable gain and with rail-to-rail input and output swing ranges. When loaded by a 1 nF capacitor, it consumes 25.35 μW to achieve a gain-bandwidth product of 100 kHz with measured IIP3 of 39.21 dBV and a slew rate of 0.5V/ μs.

 

A CMOS capsaicin concentration converter with auto-sensitivity control circuits is newly used for sensing Scoville scale applications. The proposed converter can transform capsaicin concentration into duty cycle linearly. In addition, the auto-sensitivity control circuits could automatically adjust the sensitivities under different capsaicin concentration intervals. For some patients, under low capsaicin concentration, harmful issues become an important issue for human body. With this functionality of auto-sensitivity control circuits, it can detect capsaicin concentration more sensitivity under low capsaicin concentration. The input differential voltage range of this proposed converter was from 0.1 to 1.4 V, and the corresponding range of output duty cycle was 12.223 to 95.555 %. The sensitivities of the whole system were 0.064, 0.039, 0.032, 0.021, and 0.007 %/SHU. The proposed chip could be used for detecting capsaicin concentration applications.

 

* Abstract is not available.

 

This paper presents a readout circuit, which is composed of transimpedance, programmable gain amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC), for piezoelectric accelerometer. The proposed readout circuit achieves a high linearity and low power consumption by optimizing each operational amplifier according to the linearity requirement of the whole system. The differential architecture is adopted to deal with the sensed signal for the purposes of reducing the common mode noise. A SAR ADC is used to convert the analog signal to its corresponding digital code, so the sensed signal can analyze in the digital domain. For proving the proposed design, a test chip is implemented in a 0.18 μm CMOS process. At 1.8 V supply voltage and 100kS/s sampling rate, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.74 dB and a corresponding effective number of bits (ENOB) of 9.47 bit for a Nyquist input. The total power consumption is 1.9 μW, resulting a figure of merit (FoM) of 27.2 fJ/conversion-step. Combining with the piezoelectric accelerometer, the accelerometer system can achieve 5 kHz bandwidth with a 154 mv/g sensitivity and the linearity is 0.9956.

 

Neuromorphic engineering refers to modeling nervous systems and realizing the model as a system-on-a-chip (SoC). This paper presents a neuromorphic chip fabricated by the standard CMOS 28nm technology, occupying a chip area of 4.5mm2. It provides 32 input neurons, 32 output neurons, and 32x32 synapses. Each synapse has its weight stored in 8-bit static random access memory (SRAM), and the weight is adaptable online by the spike-time-dependent plasticity (STDP) learning rule. The system architecture, sub-circuits architecture, and pilot measurement results are presented and discussed in this paper.

 

Parallelization is a common design practice for throughput improvement on multicore systems. However, the existing operating systems’ schedulers for CNN inference essentially divide the computational tasks of each convolution layer onto different CPU cores and cause significant inter-core feature-map data movement. Therefore, the overall performance is often degraded. In this paper, we propose a pipeline-based scheduler for convolution neural network inference parallelization with minimal feature-map data movement requirements. The experimental results show that our approach can achieve 73% performance improvement on throughput compared to the existing multi-thread scheduler.

 

The Convolutional Neural Network (CNN) has been proven its efficient to solve classification and recognition problems in recent years. However, due to the high computational complexity and high diverse dataflow, the CNN hardware implementation becomes a big design challenge. In conventional way, the designers usually implement a dedicated hardware based on specific CNN models or specific CNN layers, which decreases the design flexibility significantly. To mitigate the design challenge of CNN hardware implementation, we propose a novel Lego-based CNN design paradigm. Because each different CNN model is composed of similar computing functions with varying hyperparameters and dataflow, the design complexity depends on the interconnection between each computing function unit. Consequently, in this paper, we involve the Network-on-Chip (NoC) interconnection to connect each pre-defined computing function (e.g., convolution, pooling, etc.), which is called Neu-Lego. Due to the characteristic of high-flexible NoC interconnection, the corresponding Neu-Lego can transmit the data through packet delivery. In this way, the different large-scale and high-diverse CNN models can be composed by several interconnected Neu-Lego blocks without changing the interconnection, which increases the design flexibility. Therefore, our design has better compatibility because of the flexible on-chip interconnection. In addition, we propose a mapping algorithm to map the Lego PE to reduce the data communication on the NoC. Compared with the conventional approaches, the proposed mapping can improve 7.44% to 202.34% throughput and reduce 38.65% to 63.84% traffic latency, according to different involved CNN models and mapping algorithms.

 

* Abstract is not available.

 

This work presents a support vector machine (SVM) seizure detector that aims at epileptic seizure control with both seizure detection and on-chip model adaptation. Alternating direction method of multipliers (ADMM) is employed for highly- parallel SVM training. From the perspective of algorithm, minimum-redundancy maximum-relevance (mRMR) and low- rank approximation are exploited to reduce overall computational complexity by 99.4% while also reducing memory storage by 90.4%. From the aspect of hardware optimization, by utilizing hardware-shared configurable CORDIC-based processing element array, overall hardware complexity is reduced by 87%. The training latency is reduced by 98.6% by adopting parallel rotations and folded structure for approximate Jacobi method. The chip achieves detection performance with a 96.6% accuracy and a 0.28/hour false alarm rate within 0.71 seconds with power dissipation of 1.9 mW. Compared to other state-of-the-art seizure detectors, the proposed design achieves the shortest detection latency. It also supports real-time on-chip model adaptation with a latency of 0.78 seconds. This work achieves a 22× higher throughput and a 162× higher energy efficiency for SVM training compared to previous designs.

 

* Abstract is not available.

 

A combination of the median filter and local binary patterns feature extraction architecture is proposed in this paper. However, the filtered result will be stored in the storage element and sent to the next feature extraction. Based on both are spatial domain algorithms, using parallel and pipeline to achieve synchronous operation. Change the pixel input to column vector input and omit the storage process. Use median filters or hybrid median filters combined with local binary patterns and compare FPGA hardware resource usage. Because the two filters have different algorithms and sorting methods, the Hybrid median filter uses nearly half the hardware resources of the Median filter.

 

Autonomous micro robots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path planning processor for 2D/3D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly-exploring random tree (RRT) algorithm to ensure efficient planning on maps with a higher dimension and a higher resolution. Dual-tree planning, branch extension, and parallel expansion are adopted to reduce both computational complexity and memory requirement. A prune-and-reuse strategy is also adopted to quickly respond to dynamic scenarios. Fabricated in a 40-nm CMOS technology, the chip integrates 2M logic gates in 3.65 mm2 area. It supports path planning tasks on both 2D and 3D maps, with latencies of less than 1 and 10 ms, respectively. For a 100x100 2D map, the proposed processor dissipates 1.5 J/task at a clock frequency of 200 MHz from a 0.9-V supply. Compared to the state-of-the-art designs, the proposed path planning processor achieves a 1467 shorter processing latency with 2133 lower energy dissipation, despite the capability for larger maps.

 

* Abstract is not available.

 

Logic encryption is an IC protection technique which inserts extra logic and key inputs to hide a circuit's functionality. An encrypted circuit needs to be activated with a secret key for being functional. Recently, a tree-based encryption method was proposed to mitigate a powerful SAT-based attack method. Although the encryption method is effective, it could be vulnerable to a removal-based attack method. Thus, in this paper, we enhance the encryption method to resist the two attack methods simultaneously. We introduce a new type of tree encryption to obfuscate attackers, which is structurally identical to the original one but has different functionality. The experimental results show that the proposed method is effective for encrypting a set of benchmarks from IWLS. Additionally, compared to the state-of-the-art logic encryption methods, the proposed method provides better security for most benchmarks.

 

Uniform sampling is an important method in statistics and has various applications in model counting, system verification, algorithm design, among others. Symbolic sampling in a Boolean space is a recently proposed technique that combines sampling and symbolic representation for effective Boolean reasoning. Under the framework of symbolic sampling, we propose a method to construct compact XOR circuits achieving uniform sampling in a given Boolean space. The method is further extended to biased sampling within a focused subspace of interest. Experimental results show the effectiveness of compact sampling circuit generation and its potential to facilitate Boolean reasoning.

 

Quantum computing is greatly advanced in recent years and is expected to transform the computation paradigm in the near future. Quantum circuit simulation plays a key role in the toolchain for the development of quantum hardware and software systems. However, due to the enormous Hilbert space of quantum states, simulating quantum circuits with classical computers is extremely challenging despite notable efforts have been made. In this paper, we enhance quantum circuit simulation in two dimensions: accuracy and scalability. The former is achieved by using an algebraic representation of complex numbers; the latter is achieved by bit-slicing the number representation and replacing matrix-vector multiplication with symbolic Boolean function manipulation. Experimental results demonstrate that our method can be superior to the state-of-the-art for various quantum circuits and can simulate certain benchmark families with up to tens of thousands of qubits.