Enhancing Testability for Soft-Error Tolerance by Delay-Adjustable, Self-Testable Flip-Flop
發表編號：O13-1時間：11:10 - 11:25 |
論文編號：0006
Dave Y.-W. Lin, ChungLi Tang and Charles H.-P. Wen
Electrical and Computer Engineering, National Chiao Tung University
* Abstract is not available.
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SAFER: Single Aging-Factor Enhanced Rings as Data Annotators and Early Warners of On-line Aging Monitoring for Automotive SoCs
發表編號：O13-2時間：11:25 - 11:40 |
論文編號：0092
Jing Huang, Cho-Sheng Lin and Tsung-Chu Huang
Department of Electronics Engineering, National Changhua University of Education, Changhua, Taiwan
On-line aging monitoring can not only feedback life information but also adaptively response emergency. However, the root causes that arouse multi-symptoms are difficult to classify because aging cause regression from symptom histogram is dependent on life curriculum chip by chip, and a fatal symptom may stop learning and recording. In this paper, we first pro-pose the self-supervised technique that the last-survival aging symptom provides aging tagging for other symptoms. This paper is also the first to consider more than two symptoms for an online monitor including bit errors, small critical-path delays, clock-TSV delay, and power-TSV voltage drop. Three layers of neural network are applied to classify the symptoms by self-supervising SAFERs, which are proposed single-aging-factor-emphasized oscillating ring for NBTI, HCI and fatigue addressed effects. From experiments, about 63%-85% of learning accuracy can be achieved in the first stage. In the second stage, the SAFERs can be adaptively selected by the trained symptom detectors. Finally, all the SAFERs with the aging time and stratified sampling oscillating rings will be responsible for early warning and emergency processing.
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Testing of Configurable 8T SRAMs for In-Memory Computing
發表編號：O13-3時間：11:40 - 11:55 |
論文編號：0145
Tsai-Ling Tsai1, Jin-Fu Li1, Chun-Lung Hsu2 and Chi-Tien Sun2
1Department of Electrical Engineering, National Central University
2Information and Communications Research Lab., Industrial Technology Research Institute
* Abstract is not available.
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Phase Error Mitigation for a DLL using Tunable Phase Detector
發表編號：O13-4時間：11:55 - 12:10 |
論文編號：0175
Jun-Yu Yang and Shi-Yu Huang
Electrical Engineering Department, National Tsing Hua University
In this paper we present a method to mitigate the phase error of a cell-based Delay-Locked Loop (DLL) equipped with a phase-error monitor. We identify that a phase detector plagued by process variation is a main culprit of excessive phase error. To remedy this problem, we introduce a so-called "tunable phase detector" in a way that the process variation can be dynamically compensated during under the guidance provided by the on-chip phase-error monitor. Post-layout simulation results using a 90nm CMOS process has verified the effectiveness of this method. The phase error can be reduced by 83.9%, 41.7%, 41.0%, respectively, for a DLL injected with three different types of pseudo process variations occurring to the phase detector.
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