A 32 Gbps PAM-4 Optical Transceiver with Adaptive Equalizer and Active Back Termination in 40 nm CMOS Technology
發表編號：O11-1時間：11:10 - 11:25 |
論文編號：0199
Wei-Hsiang Ho, Yi-Hsun Hsieh and Yu-Che Chen
Institute of Electronics, National Chaio Tung University
* Abstract is not available.
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A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique
發表編號：O11-2時間：11:25 - 11:40 |
論文編號：0003
Hsiu-Hsien Ting, Cheng-Tang Chen and Tai-Cheng Lee
GIEE, NTU
A 5.25GHz subsampling PLL employing a frequency-shaped sub-sampling PD (SSPD) achieves a wide loop bandwidth to suppress a ring-VCO phase noise. Furthermore, because the proposed frequency-shaped SSPD introduces the additional left-half-plane zero in its loop transfer function, this work can extend its loop bandwidth with less stability consideration. Implemented in a 40-nm CMOS technology, it consumes 9mW from a 0.9-V supply. The RMS jitter integrated from 50kHz to 10MHz is 1.95ps.
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A 0.2–0.6-V ADPLL with a bootstrapped and forward interpolation DCO
發表編號：O11-3時間：11:40 - 11:55 |
論文編號：0161
Yu-Ping Li, Wen-Yuan Tsai and Jen-Chieh Liu
Department of Electrical Engineering, National Untied University, Taiwan
An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. An MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. This multiphase ADPLL was verified in a supply voltage range from 0.2 to 0.6 V. The test chip was implemented in a 90-nm CMOS process, and the core area was 60 × 117 μm2. The power consumptions at 1160 and 20 MHz were 912.6 μW (at 0.6 V) and 2.94 μW (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.39%.
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A Sub-Sampling Phase-Locked Loop With a Counter-Based Frequency-Locked Loop
發表編號：O11-4時間：11:55 - 12:10 |
論文編號：0034
Chia-Min Chen, Yu-Meng Hong and Tsung-Hsien Lin
Graduate Institute of Electronics Engineering, National Taiwan University
This paper presents an integer-N phase-locked loop (PLL), which achieves agile and robust frequency locking by incorporating the proposed counter-based frequency-locked loop (FLL). This PLL is fabricated in a 90-nm CMOS process. With a 20-MHz reference frequency, the measured in-band phase noise at 2.42 GHz is -110 dBc/Hz; the reference spur is -50 dBc. Operating from a 1.2-V supply, the power consumption of the PLL including the proposed FLL is 14.6 mW; when the FLL is switched off, the power consumption is reduced to 3 mW only. Under a 500-mV VCO supply perturbation, the PLL quickly returns to its stable locked frequency in about 5 μsec.
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