Oral Sessions

This digest proposes a synthetic ripple based phase-interleaving technique for multiphase constant on-time (COT) buck converter. When step-up load transient occurs, the proposed technique can automatically turn on two phases immediately to recover the energy loss without any user pre-defined load transient threshold voltage. Two-phase on-time periods linearly overlap to reduce the output voltage deviation and output capacitance requirement. Besides, an adaptive-extended TON control (AETC) mechanism is adopted to overcome the steady state switching frequency variation caused by parasitic resistances. A two phase buck converter is realized in a 0.18 µm CMOS process to verify these two techniques. The experimental results show that the phase-interleaving technique and AETC are suitable for a 12 MHz high switching frequency operation. The measured results show that, during 1 A load current step changes with 1 A/µs slew rate, the converter is able to regulate the output voltage from within 0.6 µs with less than 45 mV undershoot while the output capacitor is only 1 µF.

 

* Abstract is not available.

 

This paper presents a continuous-time delta-sigma-modulation (CT-DSM) and transient-enhanced-technique buck converter that features an integral loop filter with a superiority of oversampling and noise shaping for effective spurious-noise reduction. Furthermore, the transient-enhanced technique uses a dynamic current to accelerate the transient response. Thus, the proposed buck converter maintains a low spurious noise, low complex, and fast transient response. The buck converter is fabricated in TSMC 0.35um 2P4M CMOS process with a chip area of 1.23mm × 1.42mm. The measurement results show that the transient recovery time is 4us, 2us, and the undershoot, overshoot voltage is 30mV, 20mV, when the load current changes from 50mA to 500mA and from 500mA to 50mA. The output spectrum with a noise floor below -66dBm was obtained across all sampling frequencies. The max power efficiency is 91.4%, when the load current is 150mA and output voltage is 2.4V.

 

A hybrid supply modulator (HSM) is proposed for the envelope-tracking power amplifier (ET-PA) to improve its power-added efficiency (PAE). The proposed HSM consists of a linear amplifier (LA) and a switching amplifier (SA). The LA adopts a current-recycling OTA (CROTA) followed by an IQ-controlled class-AB output stage. The CROTA enhances gain and slew rate of the LA first stage. In the class-AB output stage, the quiescent current (IQ) is regulated to reduce its sensitivity to process and supply variations. The SA employs a zero-peaked hysteresis comparator for switching control which helps to reduce time delay of the SA control loop, and leads to better power efficiency. Measurement results shows that the HSM reaches 75.2% efficiency at 29.3-dBm output power. When tested with a commercial PA, the PAE improves by 17.3% at 22-dBm RF output power with 34.9-dB power gain.

 

* Abstract is not available.

 

A 5.25GHz subsampling PLL employing a frequency-shaped sub-sampling PD (SSPD) achieves a wide loop bandwidth to suppress a ring-VCO phase noise. Furthermore, because the proposed frequency-shaped SSPD introduces the additional left-half-plane zero in its loop transfer function, this work can extend its loop bandwidth with less stability consideration. Implemented in a 40-nm CMOS technology, it consumes 9mW from a 0.9-V supply. The RMS jitter integrated from 50kHz to 10MHz is 1.95ps.

 

An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. An MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. This multiphase ADPLL was verified in a supply voltage range from 0.2 to 0.6 V. The test chip was implemented in a 90-nm CMOS process, and the core area was 60 × 117 μm2. The power consumptions at 1160 and 20 MHz were 912.6 μW (at 0.6 V) and 2.94 μW (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.39%.

 

This paper presents an integer-N phase-locked loop (PLL), which achieves agile and robust frequency locking by incorporating the proposed counter-based frequency-locked loop (FLL). This PLL is fabricated in a 90-nm CMOS process. With a 20-MHz reference frequency, the measured in-band phase noise at 2.42 GHz is -110 dBc/Hz; the reference spur is -50 dBc. Operating from a 1.2-V supply, the power consumption of the PLL including the proposed FLL is 14.6 mW; when the FLL is switched off, the power consumption is reduced to 3 mW only. Under a 500-mV VCO supply perturbation, the PLL quickly returns to its stable locked frequency in about 5 μsec.

 

In this paper, a physically tightly coupled, logically loosely coupled, near-memory binary neural network accelerator (PTLL-BNN) is designed and fabricated. Both architecture-level and circuit-level optimizations are presented. From the perspective of processor architecture, the PTLL-BNN includes two new design choices. First, the proposed BNN accelerator is placed close to the SRAM of the embedded processors (i.e., physically tightly coupled and near-memory); thus, the extra SRAM cost that is incurred by the accelerator is as low as 0.5 KB. Second, the accelerator is a memory-mapped IO (MMIO) device (i.e., logically loosely coupled), so all embedded processors can be equipped with the proposed accelerator without the burden of changing their compilers and pipelines. From the circuit perspective, this work employs four techniques to optimize the power and costs of the accelerator. First, this design adopts a unified input-kernel-output memory instead of separate ones, which many previous works adopt. Second, the data layout that this work chooses increases the sequentiality of the SRAM accesses and reduces the buffer size of storing the intermediate values. Third, this work innovatively proposes to fuse the max-pooling, batch-normalization, and binarization layers of the BNNs to significantly reduce the hardware complexity. Finally, a novel methodology of generating the scheduler hardware of the accelerator is included. We fabricate the accelerator using the TSMC 180 nm technology. The chip measurement results reach 91 GOP/s on average (307 GOP/s at peak) at 200 MHz. The achieved GOP/s per million logic gates and GOP/s per KB SRAM are 2.6 to 237 times greater than that of previous works, respectively. We also realize an FPGA system to demonstrate the recognition of CIFAR-10/100 images using the fabricated accelerator.

 

In-memory computation is a new technique for computation acceleration in machine learning (ML). Since in-memory computation combines weight storage and computation, it can execute the convolution computation in a highly parallel fashion. In this paper, we present the design of a new computation in memory circuit based on the negative capacitance field effect transistor (NCFET). In addition, we show the advantage of this circuit by comparing its energy and execution time with the traditional CMOS–based computation in memory circuit.

 

Residue Number Systems can simultaneously solve several major problems of neural network including acceleration, power consumption, area overhead and fault tolerance. However, three major issues remain in the most recent work: (1) dynamic range inflation issue for all precision systems, (2) the equivalent issue on sign detection, magnitude comparison and overflow, and (3) long right shifts in CORDIC operations. In this paper, we propose a perfect deflation factor for approximate Chinese remainder theorem to limit the dynamic range inflation in long datapaths including typical neural networks. A systematic approach is then developed to design a low power, compact, fast and reliable neural network automatically. To our knowledge, this is the first paper presenting the efficient approximate computing for residue number system with more than 2.5 times of acceleration but without any dynamic range inflation issue.

 

* Abstract is not available.

 

* Abstract is not available.

 

On-line aging monitoring can not only feedback life information but also adaptively response emergency. However, the root causes that arouse multi-symptoms are difficult to classify because aging cause regression from symptom histogram is dependent on life curriculum chip by chip, and a fatal symptom may stop learning and recording. In this paper, we first pro-pose the self-supervised technique that the last-survival aging symptom provides aging tagging for other symptoms. This paper is also the first to consider more than two symptoms for an online monitor including bit errors, small critical-path delays, clock-TSV delay, and power-TSV voltage drop. Three layers of neural network are applied to classify the symptoms by self-supervising SAFERs, which are proposed single-aging-factor-emphasized oscillating ring for NBTI, HCI and fatigue addressed effects. From experiments, about 63%-85% of learning accuracy can be achieved in the first stage. In the second stage, the SAFERs can be adaptively selected by the trained symptom detectors. Finally, all the SAFERs with the aging time and stratified sampling oscillating rings will be responsible for early warning and emergency processing.

 

* Abstract is not available.

 

In this paper we present a method to mitigate the phase error of a cell-based Delay-Locked Loop (DLL) equipped with a phase-error monitor. We identify that a phase detector plagued by process variation is a main culprit of excessive phase error. To remedy this problem, we introduce a so-called "tunable phase detector" in a way that the process variation can be dynamically compensated during under the guidance provided by the on-chip phase-error monitor. Post-layout simulation results using a 90nm CMOS process has verified the effectiveness of this method. The phase error can be reduced by 83.9%, 41.7%, 41.0%, respectively, for a DLL injected with three different types of pseudo process variations occurring to the phase detector.