Oral Sessions

We propose a deep network, LithoNet, that can mimic the fabrication procedure by predicting the shape deformations of circuitry due to IC fabrication. By learning the shape correspondence between pairs of training images in two domains, i.e., layout design patterns and their SEM images of the product wafer thereof, given an IC layout pattern, LithoNet can predict its fabricated circuit shape. Furthermore, LithoNet can take the wafer fabrication parameters as a latent vector to model the parametric product variations. We evaluate our method using various benchmark layout patterns, and our experimental results demonstrate its effectiveness and robustness.

 

Multi-FPGA system prototyping has become popular for modern VLSI logic verification, but such a system realization is often limited by its number of inter-FPGA connections. As a result, time-division multiplexing (TDM) is employed to accommodate more inter-FPGA signals than the physical connections in a multi-FPGA system. However, the inter-FPGA signal delay induced by TDM becomes significant due to time-multiplexing. Researchers have shown that TDM ratios (signal time-multiplexing ratios) greatly affect the performance of a multi-FPGA system, and inter-FPGA routing highly affects the quality of this system. In this paper, we present an algorithm to minimize the system clock period for a multi-FPGA system considering the inter-FPGA routing topology and the timing criticality of nets. Our algorithm consists of two stages: (1) a distributed profiling scheme to generate a desired net ordering and then alleviate the routing congestion, and (2) a net-/edge-based refinement to assign TDM ratios efficiently with a strictly decreasing TDM ratios. Based on the 2019 CAD contest at ICCAD benchmarks and the contest evaluation metric with both quality and efficiency, experimental results show that our framework achieves the best overall score among all the participating teams and published works.

 

Directed self-assembly (DSA) with block copolymers (BCP) has become a promising lithography technology for generating tiny features in integrated circuits. There have been many existing studies investigating the design methodologies using cylinder-forming BCP for via/contact layer manufacturing. However, cylindrical DSA suffers from the limited natural pitch of generated holes and the displacement errors due to guiding template distortions. Consequently, only few feasible hole patterns are manufacturable with a template and the unsatisfactory yield is still one of the major concerns. On the other hand, lamellar DSA using lamella-forming BCP emerges as another solution for hole generation, which in combination with the self-aligned via (SAV) process is immune to hole displacement errors and able to produce various linear hole patterns. In this paper, we propose the first work of guiding template design for lamellar DSA by using the SAV process and multiple patterning lithography (MPL). An integer linear programming (ILP)-based approach is proposed that consider the design constraints induced by lamellar DSA with SAV. Experimental results demonstrate the optimality of the ILP-based approach.

 

Two-dimensional (2D) global routing followed by layer assignment is a common and popular strategy to obtain a good trade-off between runtime and routing performance. Yet, the huge gap between 2D routing patterns and the final 3D routing paths often results in inevitable overflow after layer assignment. State-of-the-art studies on layer assignment usually adopt dynamic programming-based approaches to sequentially find an optimal solution for each net in terms of overflow or/and the number of vias. However, a fixed assignment ordering severely restricts the solution space, and the distributed overflows can hardly be resolved with any existing refinement approach. This paper proposes a novel layer assignment framework that concurrently considers all the wire segments of nets and iteratively assigns them from the lowest available layer to the highest one. The concurrent scheme facilitates the maximal utilization of routing resource on each layer, contributing to an effective re-routing procedure that greatly reduces inevitable overflows. Experimental results show that compared to the sequential layer assignment solutions that also refined by the same re-routing procedure, the proposed framework can averagely reduce the maximum overflow in a tile by 32\% and reduce the number of tiles with overflows by 28\% with much less runtime, which shows the significant advantage of concurrent layer assignment over sequential methods.

 

In the modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, flexible vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using flexible vias may cause high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, in this paper, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. We first present a novel partitioning method based on the Voronoi diagram to handle irregular via structure. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing method to obtain the final solutions. Experimental results show that our work can achieve 100\% routability and an average of 30X speedup over the state-of-the-art work.

 

Abstract—As the power consumption of an electronic equipment changes more severe, device voltages in a modern design fluctuate significantly. Classic powerplanning only considers the static power which makes voltage supply become unstable and causes IR-drop to occur. Consideration of multiple power profiles becomes indispensable to current power network design. Hence, this paper develops an efficient and effective methodology to fix voltage violations for multiple power profiles while minimizing routability. The experimental results show that our methodology achieves promising results in industry designs and is much faster than an iterative approach.