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Fully homomorphic encryption allows computations to be performed directly on encrypted data for ensuring data privacy in untrusted servers, thus attracting much attention in cloud applications. By applying the concept of aggregate plaintext, this paper explores how to optimize the compare-and-swap operation, commonly used for sorting and searching in cloud computing, for fully homomorphic encrypted data. The resulting performance is optimized by properly arranging the operand locations, corresponding to the desired plaintext slots, and scheduling the sequence of fundamental homomorphic operations required to fulfill the compare-and-swap operation. Analytical results show that the number of homomorphic multiplications needed in the proposed compare-and-swap operation is logn + 4 for n-bit data, which is at least 16 times faster than related works for n = 64. Employing the proposed scheme can not only reduce the size of required FHE data, but also improve the total computation time of the chosen operation.

 

A stable local bit-line Static Random Access Memory (SRAM) architecture for near-threshold operation is proposed along with the low-voltage precharged and Negative Local Bit-Line (NLBL) scheme. The proposed local bit-line SRAM enhance the read stability and write ability for near-threshold operation system. The global bit-line can eliminate the leakage from bit cells and avoid bit-line leakage-induced read failures. By using the low voltage precharged, local bit-line pair gets an optimal precharge voltage which is lower than the supply voltage. Compared with traditional precharge, and low precharge voltage level has better Read Static Noise Margin (RSNM). Besides, The Negative Local Bit-Line enriches the SRAM write ability. At the write half-select condition, NLBL is controlled by the column write bit-line, so the simulated read bit cell's stability won't affect by the NLBL. The 1-Kb SRAM macros architecture is implemented based on the TSMC-40nm GP process. At 400mV and 25MHz operating frequency, the read and write energy consumption is 0.22pJ and 0.23pJ respectively.

 

* Abstract is not available.

 

A reliable and low error dual modular redundancy FIR filter with wide protection window have been proposed in this paper. We improved the feedback mechanism by using a multiplexer to recover the soft error struck module from error immediately. The recovering time of soft error struck module can be shortened 87.18%, and the output error rate can be lowered by 4.5 times.

 

This study describes the design and implementation of a 256-bit Very Long Instruction Word (VLIW) microprocessor based on the RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction slots, each of which performs fixed operational functions, to create a 256-bit long instruction format. In addition, to overcome the scarcity of a dedicated RISC-V VLIW compiler and leverage available RISC-V GNU toolchain, an integrated Instruction Scheduler dynamically schedules independent instructions into VLIW instruction format. Therefore, unlike conventional VLIWs, our proposed architecture is organized with six main stages: Fetch, Instruction Scheduler, Decode, Execute, Data Memory, Writeback. Besides, a Hazard Unit is utilized to solve data dependencies between VLIW instructions. The complete design is verified, synthesized, and implemented on Xilinx FPGA Virtex-6 (xc6vlx240t-1-ff1156). The proposed VLIW architecture obtains an average instruction-per-cycle (IPC) value of 1.344 times higher than that of single-issue pipelined RISC-V architecture. The maximum synthesis frequency achieves 83.739 (MHz) with the numbers of slice registers and LUTs of 21476 (7%) and 69572 (46%), respectively.

 

* Abstract is not available.