Oral Sessions

A 25-kHz 3rd-order continuous-time incremental sigma-delta modulator is proposed by utilizing a 5-bit successive-approximation-register (SAR) quantizer, incorporating 1st-order noise coupling (NC) and excess-loop-delay compensation (ELDC) into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). This prototype fabricated in a TSMC 40 nm LP CMOS technology measures a peak 71.98 dB SNDR at an over-sampling ratio (OSR) of 32, yielding a Schreier FoM of 160.5 dB and a Walden FoM of 1.39 pJ/conversion-step. The modulator occupies an active area smaller than 0.32 mm2 and consumes 225 μW.

 

This paper presents an 8-b, 1.6-GS/s pipelined-SAR ADC. The proposed ADC is partitioned into three stages with two passive residue transfer techniques for power saving. The proposed ADC, fabricated in a 40-nm CMOS technology, consumes 6.9 mW from a 1.1-V supply and achieves an SNDR of 38.8dB near Nyquist frequency. The figure of merit (FoM) is 62.8 fJ/conversion-step and its active area is 0.032 mm^2.

 

* Abstract is not available.

 

A 16-bit successive approximation register analog-to-digital converter (ADC) is presented achieving superior spurious-free dynamic range (SFDR). This ADC uses VCM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to improve the DAC linearity. A prototype ADC is fabricated in 180-nm CMOS and occupies an active area of 0.52 mm^2. At 500 kS/s, it consumes a total power of 633 uW from a supply of 1.5 V. The measured differential and integral nonlinearity are −0.65/+0.9 and −2.7/+2.5 LSB, respectively. With 1 kHz input, the measured SNDR and SFDR are 77.9 dB and 102 dB, respectively. The effective number of bits is 12.7, equivalent to a Scherier figure-of-merit of 165 dB

 

This paper presents a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with 2-bit reference voltage ripple suppression. The proposed SAR ADC adopts two extra capacitance arrays to create the opposite ripple according to the most significant bit (MSB) and MSB-1. Then a four-input comparator is utilized to cancel the ripple on the main capacitive DAC coupled by the unstable reference voltage. The prototyped ADC is fabricated in 90nm CMOS technology with a core area of 0.088mm2. At 1V supply voltage and 3MS/s sampling rate, the implemented ADC achieves a SNDR of 62.69 dB with a corresponding ENOB of 10.12 bits. The resulting figure-of-merit (FoM) is 11.6 fJ/conversion-step. In addition, the ADC could reduce the influence of reference voltage ripple about 4 times.

 

High resolution wide bandwidth applications require power-efficient high-accuracy data converters. Multi-Stage Noise-Shaping (MASH) is a useful technique for the design of stable high-order ΔΣ modulators. In this paper, we propose a two-step MASH incremental ADC (IADC). In the first step it performs a third-order coarse quantization. Re-using the same hardware, in the second step the circuit performs fine quantization as a second-order IADC. Thus, it achieves fifth-order noise shaping with only three amplifiers. For a low oversampling ratio OSR = 32, the signal-to-noise ratio can be boosted by about 30 dB. The scheme is suitable for wide bandwidth applications.