A Power-Efficient Reconfigurable OTA-C Filter for Low-Frequency Biomedical and Applications
發表編號：O2-1時間：13:40 - 13:55 |
論文編號：0063
Yi-Heng Wu, Zu-Jia Lo, Bipasha Nath, Yuan-Chuan Wang, Hui-Chun Huang and Sheng-Yu Peng
Department of Electrical Engineering, National Taiwan University of Science and Technology
* Abstract is not available.
|
|
A 12-bit 350-kS/s Column-Parallel Single-Slope ADC Readout Circuit Using Charge-Pump Phase-Locked Loop and Double-Edge Triggered Gray Code Counter
發表編號：O2-2時間：13:55 - 14:10 |
論文編號：0170
Yu-Tang Shen, Chi-Chun Chang, Yu-Hsiang Huang, Min-Yang Chiu, Guan-Cheng Chen and Chih-Cheng Hsieh
Department of Electrical Engineering, National Tsing Hua University
* Abstract is not available.
|
|
A Novel Low-Power BPSK Demodulator for Communications in Wireless Power Systems
發表編號：O2-3時間：14:10 - 14:25 |
論文編號：0139
Chi-Yi Lo and Hao-Chiao Hong
Institute of Electrical and Computer Engineering, National Chiao Tung University
* Abstract is not available.
|
|
A 3.5-GHz 685-Mb/s OOK Modulator with Loop Matching Technique in 90-nm CMOS
發表編號：O2-4時間：14:25 - 14:40 |
論文編號：0105
Yi-Chen Lu, Chih-Hong Chang and Yi-Jan Emery Chen
Graduate Institute of Electronics Engineering, National Taiwan University
* Abstract is not available.
|
|
A 91 – 109 GHz Frequency Doubler with Enhanced Fundamental Rejection in 90-nm CMOS
發表編號：O2-5時間：14:40 - 14:55 |
論文編號：0047
Ho-Chun Chang1, Yu-Wei Cheng1, Chia-Cheng Tsai2, Yung-Shun Huang1, Hong-Shen Chen2 and Jenny Yi-Chun Liu1
1Inst. Of Electronic Engineering, National Tsing Hua University
2Department Of Electrical Engineering, National Tsing Hua University
A W-band frequency doubler is proposed and demonstrated in a 90-nm CMOS technology. Differential output signals are obtained at the drain and source terminals with validated phase balance, which is seldom demonstrated in high frequency operations above 67 GHz. The input network of the circuit exhibits diverse reflections for the fundamental and second harmonic frequencies with respect to the doubler, enhancing the first harmonic rejection ratio better than 30 dB. The proposed frequency doubler shows a differential conversion gain of –8.6 dB with a 3-dB bandwidth from 91 to 109 GHz. A maximum output power larger than –5 dBm is measured to provide a sufficient power level as the local frequency signal in the transceiver design.
|
|
A 19 μW, 50 kS/s, 0.008-400V/s Scan-Rate, Cyclic Voltammetric CMOS Readout Interface with Current Feedback and On-Chip Pattern Generation
發表編號：O2-6時間：14:55 - 15:10 |
論文編號：0068
Shao-Yung Lu, Yung-Hua Yeh and Yu-Te Liao
Department of Electrical and Computer Engineering, National Chiao Tung University
* Abstract is not available.
|
|