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A W-band frequency doubler is proposed and demonstrated in a 90-nm CMOS technology. Differential output signals are obtained at the drain and source terminals with validated phase balance, which is seldom demonstrated in high frequency operations above 67 GHz. The input network of the circuit exhibits diverse reflections for the fundamental and second harmonic frequencies with respect to the doubler, enhancing the first harmonic rejection ratio better than 30 dB. The proposed frequency doubler shows a differential conversion gain of –8.6 dB with a 3-dB bandwidth from 91 to 109 GHz. A maximum output power larger than –5 dBm is measured to provide a sufficient power level as the local frequency signal in the transceiver design.

 

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A 25-kHz 3rd-order continuous-time incremental sigma-delta modulator is proposed by utilizing a 5-bit successive-approximation-register (SAR) quantizer, incorporating 1st-order noise coupling (NC) and excess-loop-delay compensation (ELDC) into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). This prototype fabricated in a TSMC 40 nm LP CMOS technology measures a peak 71.98 dB SNDR at an over-sampling ratio (OSR) of 32, yielding a Schreier FoM of 160.5 dB and a Walden FoM of 1.39 pJ/conversion-step. The modulator occupies an active area smaller than 0.32 mm2 and consumes 225 μW.

 

This paper presents an 8-b, 1.6-GS/s pipelined-SAR ADC. The proposed ADC is partitioned into three stages with two passive residue transfer techniques for power saving. The proposed ADC, fabricated in a 40-nm CMOS technology, consumes 6.9 mW from a 1.1-V supply and achieves an SNDR of 38.8dB near Nyquist frequency. The figure of merit (FoM) is 62.8 fJ/conversion-step and its active area is 0.032 mm^2.

 

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A 16-bit successive approximation register analog-to-digital converter (ADC) is presented achieving superior spurious-free dynamic range (SFDR). This ADC uses VCM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to improve the DAC linearity. A prototype ADC is fabricated in 180-nm CMOS and occupies an active area of 0.52 mm^2. At 500 kS/s, it consumes a total power of 633 uW from a supply of 1.5 V. The measured differential and integral nonlinearity are −0.65/+0.9 and −2.7/+2.5 LSB, respectively. With 1 kHz input, the measured SNDR and SFDR are 77.9 dB and 102 dB, respectively. The effective number of bits is 12.7, equivalent to a Scherier figure-of-merit of 165 dB

 

This paper presents a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with 2-bit reference voltage ripple suppression. The proposed SAR ADC adopts two extra capacitance arrays to create the opposite ripple according to the most significant bit (MSB) and MSB-1. Then a four-input comparator is utilized to cancel the ripple on the main capacitive DAC coupled by the unstable reference voltage. The prototyped ADC is fabricated in 90nm CMOS technology with a core area of 0.088mm2. At 1V supply voltage and 3MS/s sampling rate, the implemented ADC achieves a SNDR of 62.69 dB with a corresponding ENOB of 10.12 bits. The resulting figure-of-merit (FoM) is 11.6 fJ/conversion-step. In addition, the ADC could reduce the influence of reference voltage ripple about 4 times.

 

High resolution wide bandwidth applications require power-efficient high-accuracy data converters. Multi-Stage Noise-Shaping (MASH) is a useful technique for the design of stable high-order ΔΣ modulators. In this paper, we propose a two-step MASH incremental ADC (IADC). In the first step it performs a third-order coarse quantization. Re-using the same hardware, in the second step the circuit performs fine quantization as a second-order IADC. Thus, it achieves fifth-order noise shaping with only three amplifiers. For a low oversampling ratio OSR = 32, the signal-to-noise ratio can be boosted by about 30 dB. The scheme is suitable for wide bandwidth applications.

 

Recently, deep learning-assisted communication systems have achieved many eye-catching results and attracted more and more researchers in this emerging field. Instead of completely replacing the functional blocks of communication systems with neural networks, a hybrid manner of BCJRNet symbol detection is proposed to combine the advantages of the BCJR algorithm and neural networks. However, its separate block design not only degrades the system performance but also results in additional hardware complexity. In this work, we propose a BCJR receiver for joint symbol detection and channel decoding. It can simultaneously utilize the trellis diagram and channel state information for a more accurate calculation of branch probability and thus achieve global optimum with 2.3 dB gain over separate block design. Furthermore, a dedicated neural network model is proposed to replace the channel-model-based computation of the BCJR receiver, which can avoid the requirements of perfect CSI and is more robust under CSI uncertainty with 1.0 dB gain.

 

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This paper presents a human body communication (HBC) system design able to transmit the real-time data stream of a wearable electrocardiogram (ECG) device to a wearable Photoplethysmogram (PPG) device. The proposed system used conductive fabric to replace standard electrodes for HBC and build a bridge with smart clothing technologies. The transmission of the ECG from the chest to wrist reached an average accuracy of 97.1% tested for three typical cardiovascular monitoring positions. The fabric used to integrate and demonstrate that HBC can be considered for smart clothing technology was made of 50 % silver-50 %. The effective data transfer rate was 468kbps using on-off-keying (OOK) centered at 30MHz, which corresponds to a transmission time of 51µs per ECG channel.

 

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This work develops a hybrid ECG/EMG/PPG acquisition system design that supports baseline wandering cancellation (BWC) technologies and lossless data compression (LDC). A fuzzy prediction algorithm (FPA) with a well-known Huffman encoding is used to implement the proposed LDC algorithm and provides a better data compression ratio (CR) to 2.72 on average according to the evaluation of 48 patterns for MIT-BIH arrhythmia database. Additionally, the proposed moving average filter (MAF) design for BWC greatly saves the total number of additions by 97.7% compared with the traditional method. For practical circuit design, the instrumentation amplifier, right-leg driven circuit, band-pass filter, band-stop filter, Atmega328p, Bluetooth 4.0 into a PCB layout of 5×5 cm2 with a lithium battery (1000mAh) which provides 29.1 hours continuous monitoring. Finally, the hardware cost of the proposed design only takes 35.32 USD and is very suitable for future applications.

 

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Fully homomorphic encryption allows computations to be performed directly on encrypted data for ensuring data privacy in untrusted servers, thus attracting much attention in cloud applications. By applying the concept of aggregate plaintext, this paper explores how to optimize the compare-and-swap operation, commonly used for sorting and searching in cloud computing, for fully homomorphic encrypted data. The resulting performance is optimized by properly arranging the operand locations, corresponding to the desired plaintext slots, and scheduling the sequence of fundamental homomorphic operations required to fulfill the compare-and-swap operation. Analytical results show that the number of homomorphic multiplications needed in the proposed compare-and-swap operation is logn + 4 for n-bit data, which is at least 16 times faster than related works for n = 64. Employing the proposed scheme can not only reduce the size of required FHE data, but also improve the total computation time of the chosen operation.

 

A stable local bit-line Static Random Access Memory (SRAM) architecture for near-threshold operation is proposed along with the low-voltage precharged and Negative Local Bit-Line (NLBL) scheme. The proposed local bit-line SRAM enhance the read stability and write ability for near-threshold operation system. The global bit-line can eliminate the leakage from bit cells and avoid bit-line leakage-induced read failures. By using the low voltage precharged, local bit-line pair gets an optimal precharge voltage which is lower than the supply voltage. Compared with traditional precharge, and low precharge voltage level has better Read Static Noise Margin (RSNM). Besides, The Negative Local Bit-Line enriches the SRAM write ability. At the write half-select condition, NLBL is controlled by the column write bit-line, so the simulated read bit cell's stability won't affect by the NLBL. The 1-Kb SRAM macros architecture is implemented based on the TSMC-40nm GP process. At 400mV and 25MHz operating frequency, the read and write energy consumption is 0.22pJ and 0.23pJ respectively.

 

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A reliable and low error dual modular redundancy FIR filter with wide protection window have been proposed in this paper. We improved the feedback mechanism by using a multiplexer to recover the soft error struck module from error immediately. The recovering time of soft error struck module can be shortened 87.18%, and the output error rate can be lowered by 4.5 times.

 

This study describes the design and implementation of a 256-bit Very Long Instruction Word (VLIW) microprocessor based on the RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction slots, each of which performs fixed operational functions, to create a 256-bit long instruction format. In addition, to overcome the scarcity of a dedicated RISC-V VLIW compiler and leverage available RISC-V GNU toolchain, an integrated Instruction Scheduler dynamically schedules independent instructions into VLIW instruction format. Therefore, unlike conventional VLIWs, our proposed architecture is organized with six main stages: Fetch, Instruction Scheduler, Decode, Execute, Data Memory, Writeback. Besides, a Hazard Unit is utilized to solve data dependencies between VLIW instructions. The complete design is verified, synthesized, and implemented on Xilinx FPGA Virtex-6 (xc6vlx240t-1-ff1156). The proposed VLIW architecture obtains an average instruction-per-cycle (IPC) value of 1.344 times higher than that of single-issue pipelined RISC-V architecture. The maximum synthesis frequency achieves 83.739 (MHz) with the numbers of slice registers and LUTs of 21476 (7%) and 69572 (46%), respectively.

 

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We propose a deep network, LithoNet, that can mimic the fabrication procedure by predicting the shape deformations of circuitry due to IC fabrication. By learning the shape correspondence between pairs of training images in two domains, i.e., layout design patterns and their SEM images of the product wafer thereof, given an IC layout pattern, LithoNet can predict its fabricated circuit shape. Furthermore, LithoNet can take the wafer fabrication parameters as a latent vector to model the parametric product variations. We evaluate our method using various benchmark layout patterns, and our experimental results demonstrate its effectiveness and robustness.

 

Multi-FPGA system prototyping has become popular for modern VLSI logic verification, but such a system realization is often limited by its number of inter-FPGA connections. As a result, time-division multiplexing (TDM) is employed to accommodate more inter-FPGA signals than the physical connections in a multi-FPGA system. However, the inter-FPGA signal delay induced by TDM becomes significant due to time-multiplexing. Researchers have shown that TDM ratios (signal time-multiplexing ratios) greatly affect the performance of a multi-FPGA system, and inter-FPGA routing highly affects the quality of this system. In this paper, we present an algorithm to minimize the system clock period for a multi-FPGA system considering the inter-FPGA routing topology and the timing criticality of nets. Our algorithm consists of two stages: (1) a distributed profiling scheme to generate a desired net ordering and then alleviate the routing congestion, and (2) a net-/edge-based refinement to assign TDM ratios efficiently with a strictly decreasing TDM ratios. Based on the 2019 CAD contest at ICCAD benchmarks and the contest evaluation metric with both quality and efficiency, experimental results show that our framework achieves the best overall score among all the participating teams and published works.

 

Directed self-assembly (DSA) with block copolymers (BCP) has become a promising lithography technology for generating tiny features in integrated circuits. There have been many existing studies investigating the design methodologies using cylinder-forming BCP for via/contact layer manufacturing. However, cylindrical DSA suffers from the limited natural pitch of generated holes and the displacement errors due to guiding template distortions. Consequently, only few feasible hole patterns are manufacturable with a template and the unsatisfactory yield is still one of the major concerns. On the other hand, lamellar DSA using lamella-forming BCP emerges as another solution for hole generation, which in combination with the self-aligned via (SAV) process is immune to hole displacement errors and able to produce various linear hole patterns. In this paper, we propose the first work of guiding template design for lamellar DSA by using the SAV process and multiple patterning lithography (MPL). An integer linear programming (ILP)-based approach is proposed that consider the design constraints induced by lamellar DSA with SAV. Experimental results demonstrate the optimality of the ILP-based approach.

 

Two-dimensional (2D) global routing followed by layer assignment is a common and popular strategy to obtain a good trade-off between runtime and routing performance. Yet, the huge gap between 2D routing patterns and the final 3D routing paths often results in inevitable overflow after layer assignment. State-of-the-art studies on layer assignment usually adopt dynamic programming-based approaches to sequentially find an optimal solution for each net in terms of overflow or/and the number of vias. However, a fixed assignment ordering severely restricts the solution space, and the distributed overflows can hardly be resolved with any existing refinement approach. This paper proposes a novel layer assignment framework that concurrently considers all the wire segments of nets and iteratively assigns them from the lowest available layer to the highest one. The concurrent scheme facilitates the maximal utilization of routing resource on each layer, contributing to an effective re-routing procedure that greatly reduces inevitable overflows. Experimental results show that compared to the sequential layer assignment solutions that also refined by the same re-routing procedure, the proposed framework can averagely reduce the maximum overflow in a tile by 32\% and reduce the number of tiles with overflows by 28\% with much less runtime, which shows the significant advantage of concurrent layer assignment over sequential methods.

 

In the modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, flexible vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using flexible vias may cause high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, in this paper, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. We first present a novel partitioning method based on the Voronoi diagram to handle irregular via structure. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing method to obtain the final solutions. Experimental results show that our work can achieve 100\% routability and an average of 30X speedup over the state-of-the-art work.

 

Abstract—As the power consumption of an electronic equipment changes more severe, device voltages in a modern design fluctuate significantly. Classic powerplanning only considers the static power which makes voltage supply become unstable and causes IR-drop to occur. Consideration of multiple power profiles becomes indispensable to current power network design. Hence, this paper develops an efficient and effective methodology to fix voltage violations for multiple power profiles while minimizing routability. The experimental results show that our methodology achieves promising results in industry designs and is much faster than an iterative approach.

 

Brain-inspired Hyperdimensional (HD) computing is an emerging technique for cognitive tasks in the field of low-power design. As an energy-efficient and fast learning computational paradigm, HD computing has shown great success in many real-world applications. However, an HD model incrementally trained on multiple tasks suffers from the negative impacts of catastrophic forgetting. The model forgets the knowledge learned from previous tasks and only focuses on the current one. To the best of our knowledge, no study has been conducted to investigate the feasibility of applying multi-task learning to HD computing. In this paper, we propose Task-Projected Hyperdimensional Computing (TP-HDC) to make the HD model simultaneously support multiple tasks by exploiting the redundant dimensionality in the hyperspace. To mitigate the interferences between different tasks, we project each task into a separate subspace for learning. Compared with the baseline method, our approach efficiently utilizes the unused capacity in the hyperspace and shows a 12.8% improvement in averaged accuracy with negligible memory overhead.

 

Multimedia displays are generally used nowadays. With different display panels and wide range of input source, image scaling techniques are indispensable in order to convert image sources from input resolution to output resolution. Super-resolution (SR) was used to improve the scaling quality through different computations. However, in some special cases, such as overexposed or underexposed images, the image details still can’t be recovered well through complex SR scaling. In this paper, we discuss the extremely exposed image processing and propose a lightweight deep learning architecture to enhance the extremely exposed image scaling quality.

 

Object detection obtains huge improvement after adopting deep learning technique. However, deep learning technique requires extremely high computation complexity and heavy DRAM (Dynamic Random Access Memory) bandwidth requirements, which blocks the deployment over various kinds of platforms. This paper provides a distance-aware technique for object detection that can adjust the required computation complexity and DRAM access amount according to several different searching distances. According to our analysis, the perception system can save up to 34.2% and 20.1% of computation complexity and DRAM access amount, respectively, for detecting near field objects when compared to the full range detection. The proposed distance-aware technique can let the deep learning neural networks adjust the required computation complexity and DRAM access amount according to several different searching distances. Unlike other works that emphasized on removing dummy computations and DRAM access from the network by trading-off limited detection accuracy, we propose a human natural way for machines to follow. By following this way, the machines search the surrounded environment in a priority scheme, from near to far, just like humans.

 

This work presents an intelligent system platform design for hybrid mixer and digital equalizer using speech recognition technology instead of manual turning the knobs. The proposed platform provides both touch control and voice control for adjusting sound sources, volume, and the effects of equalization and reverberation using a smartphone APP. For speech recognition, a Google cloud service releases a strong function library, i.e. “SpeechRecongnizer class”, which helps convert short-time speech into a string. Then, a useful control message extracted from a string segmentation and comparison processing is transmitted to a data transfer controller (DTC) by a Bluetooth module. To connect the smartphone and the proposed DTC, we especially define a self-defined Bluetooth Packet Format (SBPF) into the Bluetooth5.0 protocol. The proposed SBPF also adopts Cyclic Redundancy Check (CRC, CRC-16-CCITT), and acknowledgment mechanism to improve the transmission correctness and data integrity. For the proposed hybrid mixer and digital equalizer, a Digital Signal Processor (DSP KT0707) is employed to be the kernel of this intelligent system platform and is connected to the proposed DTC by I2C protocol. Compared to traditional audio mixer designs, a man who is responsible for public address system (PA) can more quickly predominate the effects of the ambient sound field by using voice/touch control via the proposed APP, and enhances listeners’ feelings about live band performance.

 

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